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publication# 080180 rev: c amendment: / 0 issue date: may 1999 am79484 subscriber line interface circuit distinctive characteristics ideal for long-loop applications low standby power (45 mw) ?40 v to ?58 v battery operation on-hook transmission tip open state for ground-start lines two-wire impedance set by single external impedance programmable constant-current feed programmable loop-detect threshold current gain = 200 polarity reversal option available on-chip thermal management (tmg) feature on-chip ring and test relay driver and relay snubber circuits block diagram c4 c3 two-wire interface hpa hpb input decoder and control detector ring-trip detector power-feed controller da db bgnd vcc vneg rdc agnd/dgnd vbat a(tip) b(ring) ringout det cas testout rd tmg relay driver ring relay driver c1 rsn signal transmission vtx c2 off-hook detector ground-key e0 e1
2 am79484 data sheet ordering information standard products legerity standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the elements below. am79484 j c temperature range c = commercial (0 c to 70 c)* package type j = 32-pin plastic leaded chip carrier (pl 032) device number/description am79484 subscriber line interface circuit ?1 performance grade option ?1 = 52 db longitudinal balance, polarity reversal ?2 = 63 db longitudinal balance, polarity reversal ?3 = 52 db longitudinal balance, no polarity reversal ?4 = 63 db longitudinal balance, no polarity reversal note: * functionality of the device from 0c to +70c is guaranteed by production testing. performance from ?40c to +85c is guaranteed by characterization and periodic sampling of production units. valid combinations am79484 ?1 jc ?2 ?3 ?4 valid combinations valid combinations list configurations planned to be supported in volume for this device. consult the local legerity sales office to confirm availability of specific valid combinations, to check on newly released combinations, and to obtain additional data on legerity?s standard military grade products.
slic products 3 connection diagram top view 4 3 2 1 32 31 30 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 vbat da hpb hpa vee rsn ringout 26 27 28 29 nc nc agnd/dgnd c2 32-pin plcc a(tip) b(ring) det c1 cas rdc nc vcc bgnd db nc tmg e1 c3 c4 nc rd vtx rsvd e0 testout notes: 1. pin 1 is marked for orientation. 2. nc = no connect 3. rsvd = reserved. do not connect to this pin.
4 am79484 data sheet pin descriptions pin names type description agnd/dgnd ground analog and digital ground are connected internally to a single pin. a(tip) output output of a(tip) power amplifier. bgnd ground battery (power) ground. b(ring) output output of b(ring) power amplifier. c4 ? c1 input decoder. slic control pins. ttl compatible. c4 is msb and c1 is lsb. cas capacitor anti-saturation. pin for capacitor to filter reference voltage when operating in anti- saturation region. da input ring-trip negative. negative input to ring-trip comparator. db input ring-trip positive. positive input to ring-trip comparator. det output switchhook detector. logic low indicates that the selected detector is tripped. c3 ? c1 and e0 select the detector. open-collector with a built-in 15 k ? pull-up resistor. e0 input detect enable. a logic high enables det . a logic low disables det . e1 input ground-key enable. e1 low connects the ground-key or ring-trip detector to det . e1 high connects the off-hook detector or ring-trip detector to det . hpa capacitor high-pass filter. a(tip) side of high-pass filter capacitor. hpb capacitor high-pass filter. b(ring) side of high-pass filter capacitor. nc ? no connect. pin not internally connected. rd resistor detect resistor. threshold modification/filter point for the off-hook detector. rdc resistor dc feed resistor. connection point for the dc feed current programming network. the other end of the network connects to the receiver summing node (rsn). vrdc is negative for normal polarity and positive for reverse polarity. ringout output ring relay driver. open collector darlington pull down. rsn input receive summing node. the metallic current (both ac and dc) between a(tip) and b(ring) is 200 times the current flowing into this pin. the networks that program receive gain, two-wire impedance, and feed resistance connect to this node. rsvd ? this pin is reserved only for test purposes. leave unconnected. testout output test relay driver. open collector darlington pull down. tmg ? thermal management. external resistor connects between this pin and vbat to off-load power dissipation from slic. functions during normal polarity and reverse polarity states. vbat battery battery supply. connected through an external protection diode. vcc power +5 v power supply. vee power ? 5 v power supply. vtx output transmit audio. this output is a unity gain version of the a(tip) and b(ring) metallic voltage. vtx also sources the two-wire input impedance programming network.
slic products 5 absolute maximum ratings storage temperature . . . . . . . . . . . . ? 55 c to +150 c v cc with respect to agnd/dgnd . . . . ? 0.4 v to +7 v v ee with respect to agnd/dgnd . . . . +0.4 v to ? 7 v v bat with respect to agnd/dgnd: continuous . . . . . . . . . . . . . . . . . . . +0.4 v to ? 70 v 10 ms . . . . . . . . . . . . . . . . . . . . . . . +0.4 v to ? 75 v bgnd with respect to agnd/dgnd . . . .+3 v to ? 3 v a(tip) or b(ring) to bgnd: continuous . . . . . . . . . . . . . . . . . . . . ? 70 v to +1 v 10 ms (f = 0.1 hz) . . . . . . . . . . . . . . . ? 70 v to +5 v 1 s (f = 0.1 hz) . . . . . . . . . . . . . . . . . ? 80 v to +8 v 250 ns (f = 0.1 hz) . . . . . . . . . . . . . . ? 90 v to +12 v current from a(tip) or b(ring). . . . . . . . . . 150 ma ringout/testout current. . . . . . . . . . . . . . 75 ma ringout/testout voltage . . . . . . . bgnd to +7 v ringout/testout transient . . . . . bgnd to +10 v da and db inputs voltage on ring-trip inputs . . . . . . . . . . .v bat to 0 v current into ring-trip inputs . . . . . . . . . . . . 10 ma c4 ? c1, e0, e1 input voltage. . . . . . . . . . . . . ? 0.4 v to v cc + 0.4 v maximum power dissipation, continuous, t a = 70 c, no heat sink (see note): in 32-pin plcc package . . . . . . . . . . . . . . . . 1.7 w thermal data: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ja in 32-pin plcc package . . . . . . . . . . . .43 c/w typ note: thermal limiting circuitry on chip will shut down the circuit at a junction temperature of about 165 c. the device should never see this temperature, and operation above 145 c junction temperature may degrade device reliability. see the slic packaging considerations for more informa- tion. stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may effect device reliability. operating ranges commercial (c) devices ambient temperature . . . . . . . . . . . . . . 0 c to +70 c* v cc . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75 v to 5.25 v v ee . . . . . . . . . . . . . . . . . . . . . . . . ? 4.75 v to ? 5.25 v v bat . . . . . . . . . . . . . . . . . . . . . . . . . . ? 40 v to ? 58 v agnd/dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v bgnd with respect to agnd/dgnd . . . . . . . . . . . . ? 100 mv to +100 mv load resistance on vtx to ground . . . . . . . 10 k ? min the operating ranges define those limits between which the functionality of the device is guaranteed. * functionality of the device from 0 c to +70 c is guaranteed by production testing. performance from ? 40 c to +85 c is guaranteed by characterization and periodic sampling of production units. steady state operation at t a = 70 c is guaranteed by testing at 90 c and guard banding.
6 am79484 data sheet electrical characteristics description test conditions (see note 1) min typ max unit note transmission performance 2-wire return loss 200 hz to 3.4 khz 26 db 1, 4, 7 analog output (v tx ) impedance 3 20 ? 4 analog (v tx ) output offset voltage 0 c to +70 c ? 40 c to +85 c ? 40 ? 50 +40 +50 mv ? 4 overload level, 2 wire and 4 wire active state 2.5 vpk 2a overload level on hook, r lac = 900 ? 1.18 vrms 2b thd, total harmonic distortion 0 dbm 0 dbm, r ldc = 2030 ? , bat = ? 42.5 v +7 dbm ? 64 ? 45 ? 55 ? 50 ? 40 db 5 ? 5 thd, on hook +1 dbm, r lac = 900 ? ? 36 5 longitudinal capability (see test circuit c) longitudinal to metallic l-t, l-4 200 hz to 1 khz ? 1, ? 3* 52 70 200 hz to 1 khz ? 2, ? 4* normal polarity 63 200 hz to 1 khz ? 2* reverse polarity 58 200 hz to 1 khz ? 2, ? 4* ? 40 c to +85 c 58 4 1 khz to 3.4 khz ? 1, ? 3* 52 1 khz to 3.4 khz ? 2, ? 4* 58 1 khz to 3.4 khz ? 40 c to +85 c 54 4 longitudinal signal generation 4-l 200 hz to 800 hz normal polarity 40 db longitudinal current per pin active state standby state 8.5 8.5 27 27 marms longitudinal impedance at a or b 0 hz to 100 hz 25 35 ? /pin idle channel noise c-message weighted noise +25 c to +85 c ? 40 c to +25 c +7 +10 +12 dbrnc ? 4 psophometric weighted noise +25 c to +85 c ? 40 c to +25 c ? 83 ? 80 ? 78 dbmp insertion loss (2- to 4-wire and 4- to 2-wire, see test circuits a and b) gain accuracy 0 dbm, 1 khz 0 c to +70 c 0 dbm, 1 khz ? 40 c to +85 c on hook, oht state ? 0.15 ? 0.20 ? 0.35 +0.15 +0.20 +0.35 db ? 4 4 gain accuracy over frequency relative to 1 khz 300 hz to 3.4 khz 0 c to +70 c 300 hz to 3.4 khz ? 40 c to +85 c ? 0.10 ? 0.15 +0.10 +0.15 5 4 gain tracking relative to 0 dbm +3 dbm to ? 55 dbm 0 c to +70 c +3 dbm to ? 55 dbm ? 40 c to +85 c +3 dbm, bat = ? 42.5 v, r ldc = 2030 ? on hook ? 0.10 ? 0.15 ? 0.30 ? 0.35 +0.10 +0.15 +0.30 +0.35 ? 4 ? ? note: * performance grade
slic products 7 electrical specifications (continued) description test conditions (see note 1) min typ max unit note balance return signal (4-wire to 4-wire) gain accuracy ref: 0 dbm, 1 khz 0 c to +70 c ref: 0 dbm, 1 khz ? 40 c to +85 c ? 0.15 ? 0.20 +0.15 +0.20 db 3 4 gain accuracy over frequency 300 hz to 3400 hz 0 c to +70 c 300 hz to 3400 hz ? 40 c to +85 c ? 0.10 ? 0.15 +0.10 +0.15 3 4 gain tracking relative to 0 dbm +3 dbm to ? 55 dbm 0 c to +70 c +3 dbm to ? 55 dbm ? 40 c to +85 c ? 0.10 ? 0.15 +0.10 +0.15 ? 4 group delay 0 dbm, 1 khz 4 s 4, 7 line characteristics voltage on tmg pin constant-current region v tmg 8 i l , short loops, active or oht state 20 22 24 ma i l , long loops, active state r ldc = 2030 ? , bat = ? 42.5 v, t a = 25 c 18 18.6 i l , accuracy, standby state t a = 25 c constant-current region 0.8i l 16 i l 22 1.2i l 39 i l , loop current, tip open state r l = 0 ? , v a = 0 ? to v a = v bat b to ground v bat = ? 56.5 v, r = 2.2 k ? , b to gnd 0 23 22 100 45 24.5 a ma ma i l , loop current, open circuit state r l = 0 ? 100 a i l lim active, a and b to gnd 95 120 ma v a , active, ground-start signaling a to ? 48 v = 7 k ? , b to gnd = 100 ? ? 7.5 ? 5 v 4 v ab , open circuit voltage bat = ? 52 v ? 42.75 ? 45.7 a lead impedance, tip open state v a = 0 v to v a = v bat 150 k 10 m ? 4 power supply rejection ratio (v ripple = 100 mvrms), active normal state v cc 50 hz to 3400 hz 500 hz to 3000 hz 30 35 40 db 5 v ee 50 hz to 3400 hz 500 hz to 3000 hz 28 30 35 v bat 50 hz to 3400 hz 500 hz to 3000 hz 28 45 50 effective internal resistance cas pin to gnd 85 170 255 k ? 4 control lead feed through 50 hz to 3400 hz on c1, c2, or c3 35 50 db i l v bat 3 v ? r l 400 + ------------------------------ - =
8 am79484 data sheet electrical specifications (continued) description test conditions (see note 1) min typ max unit note power dissipation on hook, open circuit state 25 70 mw on hook, standby state 45 85 on hook, oht state 180 270 on hook, active state r tmg = open r tmg = 2500 ? 180 195 270 300 4 off hook, standby state 860 1100 off hook, oht state r l = 300 ? , r tmg = open 1000 1300 off hook, active state r l = 300 ? , r tmg = 2500 ? 450 800 supply currents, battery = ? 58 v icc, on-hook v cc supply current open circuit state oht state standby state active state, bat = ? 48 v 1.7 7.0 3.0 6.3 2.5 8.5 3.5 8.5 ma iee, on-hook v ee supply current open circuit state oht state standby state active state, bat = ? 48 v 0.7 2.0 0.77 2.1 2.0 3.5 2.0 5.0 ibat, on-hook v bat supply current open circuit state oht state standby state active state, bat = ? 48 v 0.18 1.9 0.45 4.2 1.0 4.7 1.5 5.7 rfi rejection rfi rejection 100 khz to 30 mhz, (see figure e) 1.0 mvrms 4 receive summing node (rsn) rsn dc voltage i rsn = 0 ma 0 v 4 logic inputs (c4 ? c1, e0, e1) v ih , input high voltage 2.0 v v il , input low voltage 0.8 i ih , input high current ? 75 40 a i il , input low current c4 ? c1, e0, e1 ? 400 logic output (det ) v ol , output low voltage iout = 0.3 ma, 15 k ? to v cc 0.40 v v oh , output high voltage iout = ? 0.1 ma, 15 k ? to v cc 2.4 ring-trip detector input (da, db) bias current ? 20 ? 5na4 offset voltage source resistance = 2 m ? ? 50 0 +50 mv 6 offset voltage source resistance mismatch = 3 m ? ? 50 0 +50 4
slic products 9 electrical specifications (continued) relay driver schematics description test conditions (see note 1) min typ max unit note relay driver output (ringout) on voltage i ol = 41 ma +0.35 +1.00 v off leakage v oh = +5 v 100 a zener breakover i z = 100 a 6 7.2 v zener on voltage i z = 30 ma 10 test driver output (testout) on voltage i ol = 81.5 ma +0.8 +1.50 v off leakage v oh = +5 v 100 a zener breakover i z = 100 a 6 7.2 v zener on voltage i z = 80 ma 14 detector thresholds i t , loop-detect threshold tolerance r d = 35.4 k ? , active standby 330/r d 330/r d 375/r d 375/r d 420/r d 420/r d a i t , ground-key detect threshold tip open, b lead only, e1 = 0 7.5 10 14 ma ringout bgnd testout agnd
10 am79484 data sheet notes: 1. unless otherwise noted, test conditions are bat = ? 48 v, v cc = +5 v, v ee = ? 5 v, r l = 600 ? , r dc1 = r dc2 = 11.36 k ? , r d = 35.4 k ? , r tmg = 2.5 k ? , no fuse resistors, c hp = 0.2 f, c dc = 0.1 f, c cas = 0.1 f, two-wire ac input impedance is a 900 ? resistance synthesized by the programming network shown below. 2. a. overload level is defined when thd = 1%. b. overload level is defined when thd = 1.5%. 3. balance return signal is the signal generated at v tx by v rx . this specification assumes that the two-wire ac load impedance matches the programmed impedance. 4. not tested in production. this parameter is guaranteed by characterization or correlation to other tests. 5. this parameter is tested at 1 khz in production. performance at other frequencies is guaranteed by characterization. 6. tested with 0 ? source impedance. 2 m ? is specified for system design only. 7. group delay can be greatly reduced by using a zt network such as that shown in note 1 above. the network reduces the group delay to less than 2 s and increases 2wrl. the effect of group delay on linecard performance may also be compensated by synthesizing complex impedance with the qslac ? or dslac ? device. 8. the voltage on the tmg pin (v tmg ) is related to the voltage across the line (v ab ) when the device is in the constant-current region. the relationship between v ab and v tmg voltage is described by the following equation: v tmg = ? 0.966|v ab | ? 6.23 notes: 1. c4 logic high enables the testout relay driver. 2. e0 logic high enables the det pin. table 1. slic decoding det output state c3 c2 c1 two-wire status e1 = 1 e1 = 0 0 0 0 0 open circuit ring trip ring trip 1 0 0 1 ringing ring trip ring trip 2 0 1 0 active loop detector ground key 3 0 1 1 on-hook tx (oht) loop detector ground key 4 1 0 0 tip open loop detector ground key 5 1 0 1 standby loop detector ground key 6 1 1 0 active polarity reversal loop detector ground key 7 1 1 1 oht polarity reversal loop detector ground key c t1 = 100 pf r t1 = 90 k ? vtx rsn v rx r t2 = 90 k ? r rx = 90 k ? ~
slic products 11 table 2. user-programmable components z t is connected between the vtx and rsn pins. the fuse resistors are r f , and z 2win is the desired 2-wire ac input impedance. when computing z t , the internal current amplifier pole and any external stray capacitance between vtx and rsn must be taken into account. z rx is connected from v rx to r sn . z t is defined above, and g 42l is the desired receive gain. r dc1 , r dc2 , and c dc form the network connected to the rdc pin. r dc1 and r dc2 are approximately equal. i loop is the desired loop current in the constant-current region. r d and c d form the network connected from rd to ? 5 v, and i t is the threshold current between on hook and off hook. c cas is the regulator filter capacitor, and f c is the desired filter cut-off frequency. oht loop current (constant-current region). thermal management equations (normal active and tip open states) r tmg is connected from t mg to v bat and is used to limit power dissipation within the slic in active and tip open states only. power is dissipated in the thermal management resistor, r tmg , during active and tip open states. power is dissipated in the slic while in active and tip open states. z t 200 z 2win 2r f ? () = z rx z l g 42l ----------- 200 z t ? z t 200 z l 2r f + () + ------------------------------------------------- ? = r dc1 r dc2 500 i loop ------------- - = + c dc 1.5 ms r dc1 r dc2 + r dc1 r dc2 ------------------------------- - ? = r d 375 i t -------- - c d 0.5 ms r d ---------------- = , = c cas 1 3.4 10 5 f c ? ----------------------------- = i oht 500 r dc1 r dc2 + ------------------------------- - = r tmg v bat 6 v ? i loop ------------------------------ - p rtmg v bat 6v ? i l r l ? () ? () 2 r tmg ------------------------------------------------------------------ - = p slic v bat i l p rtmg ? r l i l () ? ? 2 0.12 w + =
12 am79484 data sheet dc feed characteristics 0 i l (ma) v ab (v) 30 60 1 2 3 1. 2. 3. v ab i l r l ' 500 r dc --------- - r l ' where r l 'r l 2r f + = , = = v ab 0.925 v bat ? 0.9 i l r dc 120 --------- - ? + = v ab 0.925 v bat ? 1.83 ? i l r dc 120 --------- - ? = r dc = r dc1 + r dc2 = 22.72 k ? bat = ? 48 v a. load line (typical) r l r dc2 a b rsn rdc slic b. feed programming feed current programmed by r dc1 and r dc2 a b i l r dc1 c dc figure 1. dc feed characteristics
slic products 13 test circuits r t r rx v ab v l r l 2 i l2-4 = 20 log (v tx / v ab ) a. two- to four-wire insertion loss a(tip) b(ring) agnd vtx rsn slic r t v ab a(tip) b(ring) agnd vtx rsn slic r l r rx v rx i l4-2 = 20 log (v ab / v rx ) brs = 20 log (v tx / v ab ) b. four- to two-wire insertion loss and balance return signal r t r rx r l 2 r l 2 v rx s1 c s2 v l v l a(tip) b(ring) agnd vtx rsn slic 1 c << r l l-4 long. bal. = ? 20 log (v tx / v l ) l-t long. bal. = ? 20 log (v ab / v l ) 4-l long. sig. gen. = ? 20 log (v l / v rx ) c. longitudinal balance r l 2 v ab s2 open, s1 closed s2 closed, s1 open
14 am79484 data sheet test circuits (continued) d. two-wire return loss test circuit r r return loss = ? 20 log (2 v m / v s ) z d : the desired impedance; e.g., the characteristic impedance of the line v m z in v s a(tip) b(ring) agnd vtx rsn slic r t2 r rx c t1 r t1 z d e. rfi test circuit 50 ? l 1 200 ? 200 ? c 1 c 2 b hf gen vtx a slic under test l 2 cax 33 nf cbx 33 nf rf 1 rf 2 50 ? 50 ? 1.5 vrms 80% amplitude modulated 100 khz to 30 mhz
slic products 15 test circuits (continued) f. am79484 test circuit battery ground analog ground digital vee vcc r d rd vtx agnd/ dgnd rsn r rx r dc2 r dc1 c dc r t rdc c3 c2 c1 ? 5 v +5 v vbat det d 1 bgnd ringout hpb c hp hpa db da a(tip) b(ring) cas c cas bat 2.2 nf 2.2 nf v tx v rx a(tip) b(ring) testout c4 e0 tmg r tmg schottky e1 ground
16 am79484 data sheet physical dimensions pl032 revision summary revision a to b within the electrical specifications, under the supply currents, changed the values for the icc, on hook vcc supply current. minor changes were made to the data sheet style and format to conform to legerity standards. revision b to c the equation in note #8 on page 10 was modified. the physical dimensions were added on page 16. .050 ref. .026 .032 top view pin 1 i.d. .485 .495 .447 .453 .585 .595 .547 .553 16-038fpo-5 pl 032 da79 6-28-94 ae side view seating plane .125 .140 .009 .015 .080 .095 .042 .056 .013 .021 .400 ref. .490 .530
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